Formal Equivalence Checking and Design Debugging

1 Introduction. - 1. 1 Problems of Interest. - 1. 2 Organization. - I Equivalence Checking. - 2 Symbolic Verification. - 3 Incremental Verification for Combinational Circuits. - 4 Incremental Verification for Sequential Circuits. - 5 AQUILA: A Local BDD-based Equivalence Verifier. - 6 Algorithm for Verifying Retimed Circuits. - 7 RTL-to-Gate Verification 123. - II Logic Debugging. - 8 Introduction to Logic Debugging. - 9 ErrorTracer: Error Diagnosis by Fault Simulation. - 10 Extension to Sequential Error Diagnosis. - 11 Incremental Logic Rectification. Language: English